data sheet no. pd60200 revb features ? floating channel designed for bootstrap operation to +600v. tolerant to negative transient voltage dv/dt immune ? gate drive supply range from 10 to 20v ? under voltage lockout for both channels ? 3.3v, 5v, and 15v input logic input compatible ? cross-conduction prevention logic ? matched propagation delay for both channels ? lower di/dt gate driver for better noise immunity ? internal 100ns dead-time ? output in phase with input half-bridge driver product summary v offset 600v max. i o +/- (min) 60 ma/130 ma v out 10 - 20v delay matching 50 ns internal deadtime 100 ns t on/off (typ.) 220/220 ns ir2304(s) & (pbf) www.irf.com 1 lin hin vcc com vb ho vs lo vcc hin lin up to 600v to load ir2304 block diagram package 8 lead soic 8-lead pdip part input logic cross- conduction prevention logic dead-time ground pins 2106/2301 com 21064 hin/lin no none vss/com 2108 internal 540ns com 21084 hin/lin yes programmable 0.54~5 s vss/com 2109/2302 internal 540ns com 21094 in/sd yes programmable 0.54~5 s vss/com 2304 hin/lin yes internal 100ns com 2106/2301/2108/2109/2302/2304 feature comparison ? available in lead-free description the ir2304(s) are a high voltage, high speed power mosfet and igbt driver with inde- pendent high and low side referenced output channels. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. the logic input is compatible with standard cmos or lsttl output, down to 3.3v logic. the output driver features a high pulse cur- rent buffer stage designed for minimum driver cross-conduction. the floating chan nel can be used to drive an n-channel power mosfet or igbt in the high side configuration which operates up to 600 volts.
ir2304(s)&(pbf) 2 www.irf.com note 1: logic operational for v s of com -5 to com +600v. logic state held for v s of com -5v to com -v bs . symbol definition min. max. units v s high side offset voltage v b - 25 v b + 0.3 v b high side floating supply voltage -0.3 625 v ho high side floating output voltage ho v s - 0.3 v b + 0.3 v cc low side and logic fixed supply voltage -0.3 25 v lo low side output voltage lo -0.3 v cc + 0.3 v in logic input voltage (hin, lin) -0.3 v cc + 0.3 com logic ground v cc -25 v cc + 0.3 dv s /dt allowable offset voltage slew rate ? 50 v/ns p d package power dissipation @ t a d +25 c 8-lead soic ? 0.625 8-lead pdip ? 1.0 rth ja thermal resistance, junction to ambient 8-lead soic ? 200 8-lead pdip ? 125 t j junction temperature ? 150 t s storage temperature -50 150 t l lead temperature (soldering, 10 seconds) ? 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com, all currents are defined positive into any lead. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. v c symbol definition min. max. units v b high side floating supply voltage v s + 10 v s + 20 v s high side floating supply offset voltage note 1 600 v ho high side (ho) output voltage v s v b v lo low side (lo) output voltage com v cc v in logic input voltage (hin, lin) com v cc v cc low side supply voltage 10 20 t a ambient temperature -40 125 c recommended operating conditions the input/output logic timing diagram is shown in figure 1. for proper operation the device should be used within the recommended conditions. the v s offset rating is tested with all supplies biased at 15v differential. v w c/w
ir2304(s)&(pbf) www.irf.com 3 symbol definition min. typ. max. units test conditions v ccuv+ v cc and v bs supply undervoltage positive going 8 8.9 9.8 v bsuv+ threshold v ccuv- v cc and v bs supply undervoltage negative going 7.4 8.2 9 v bsuv- threshold v ccuvh v cc supply undervoltage lockout hysteresis 0.3 0.7 ? v bsuvh i lk offset supply leakage current ? ? 50 v b = v s = 600v i qbs quiescent v bs supply current 20 60 150 v in = 0v or 5v i qcc quiescent v cc supply current 50 120 240 v in = 0v or 5v v ih logic ?1? input voltage 2.3 ?? v il logic ?0? input voltage ? ? 0.8 v oh high level output voltage, v bias - v o ? ? 2.8 v ol low level output voltage, v o ? ? 1.2 i in+ logic ?1? input bias current ? 5 40 v in = 5v i in- logic ?0? input bias current ? 1.0 2.0 v in = 0v i o+ output high short circuit pulse current 60 ? ? i o- output low short circuit pulsed current 130 ? ? static electrical characteristics v bias (v cc , v bs ) = 15v and t a = 25 c unless otherwise specified. the v in , v th and i in parameters are referenced to com. the v o and i o parameters are referenced to com and v s is applicable to ho and lo. v v symbol definition min. typ. max. units test conditions t on turn-on propagation delay 120 220 320 v s = 0v t off turn-off propagation delay 130 220 330 v s = 0v or 600v t r turn-on rise time 60 200 300 t f turn-off fall time 20 100 170 dt dead time 80 100 190 mt delay matching, hs & ls turn-on/off ? ? 50 dynamic electrical characteristics v bias (v cc , v bs ) = 15v, v s = com, c l = 1000 pf and t a = 25 c unless otherwise specified. v o = 0v pw d 10 s ns p a i o = 20ma ma p a
ir2304(s)&(pbf) 4 www.irf.com functional block diagram 2304 lin uv detect delay com lo vcc hin vs ho vb pulse filter hv level shifter r r s q uv detect pulse generator shoot- through prevention lead definitions symbol description v cc low side supply voltage com logic ground and low side driver return hin logic input for high side gate driver output lin logic input for low side gate driver output v b high side floating supply ho high side driver output v s high voltage floating supply return lo low side driver output
ir2304(s)&(pbf) www.irf.com 5 8 7 6 4 3 2 1 lin com hin vcc lo ho vb vs 5 8-lead pdip 8 7 6 4 3 2 1 lin com hin vcc lo ho vb vs 5 lead assignments 8-lead soic hin lin ho lo figure 1. input/output functionality diagram internal deadtime
ir2304(s)&(pbf) 6 www.irf.com figure 3. internal deadtime timing figure 2. switching time waveforms hin lin ho lo t on t r 50% 90% 10% 50% 90% 10% t off t f hin lin dt dt 90% 10% 50% 90% 10% 50% lo ho
ir2304(s)&(pbf) www.irf.com 7 01-6027 01-0021 11 (ms-012aa) 8 lead soic 87 5 65 d b e a e 6x h 0.25 [.010] a 6 4 3 12 4. out line conforms t o jede c outline ms -012aa. not e s : 1. dimens ioning & tole rancing pe r as me y14.5m-1994. 2. controlling dimens ion: millimet er 3. dime ns ions are s hown in mi lli me t e rs [inche s ]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 4. outline conforms t o jedec out line ms-012aa. 5 dime ns ion doe s not inclu de mol d prot rus ions . 6 dime ns ion doe s not inclu de mol d prot rus ions . mold protrusions not t o exce ed 0.25 [.010]. 7 dimension is the length of lead for soldering to a substrat e. mold protrusions not t o exce ed 0.15 [.006]. 0.25 [.010] c a b e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 b as ic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 bas ic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters inches min max dim 8 e c .0075 .0098 0.19 0.25 .025 b as ic 0.635 bas ic 01-6014 01-3003 01 (ms-001ab) 8-lead pdip case outlines
ir2304(s)&(pbf) 8 www.irf.com this product has been designed and qualified for the industrial market. qualification standards can be found on ir?s web site. data and specifications subject to change without notice. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 09/10/04 basic part (non-lead free) lead-free part 8-lead pdip ir2304 order ir2304 8-lead pdip ir2304 order IR2304PBF 8-lead soic ir2304s order ir2304s 8-lead soic ir2304s order ir2304spbf order information
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